1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) and a method for manufacturing the same, and more particularly, the present invention relates to a fringe field switching liquid crystal display (FFS-LCD) and a method for manufacturing the same.
2. Description of the Related Art
Generally, a fringe field switching liquid crystal display is developed so as to increase an aperture ratio and a transmittance of an in-plane switching liquid crystal display (IPS-LCD), as is described in U.S. patent application Ser. No. 09/379,031, now U.S. Pat. No. 6,281,953, issued on Aug. 28, 2001.
An FFS-LCD includes an upper substrate and a lower substrate which are separated from each other by a predetermined cell gap, a liquid crystal layer which is intervened between the upper and lower substrates, and a counter electrode and a pixel electrode which are formed on an inner surface of the lower substrate. Each of the counter electrode and the pixel electrode is made of a transparent conductive material, and a distance between the counter electrode and the pixel electrode is set to be smaller than the predetermined cell gap. According to this, a fringe field is formed between and over the electrodes.
FIG. 1 is a plan view of a lower substrate of the conventional FFS-LCD. Referring to FIG. 1, by the fact that a gate bus line 3 and a data bus line 7 are disposed on a lower substrate 1 in such a way as to be crossed with each other, a unit pixel is defined. A thin film transistor TFT is located at a place where the gate bus line 3 and the data bus line 7 are crossed with each other. A counter electrode 2 which is made from a transparent conductive material, is arranged for each unit pixel. At this time, the counter electrode 2 can be formed to have a rectangular plate-shaped or a comb-shaped contour. A common signal line 30 is disposed in a manner such that the common signal line 30 is brought into contact with the counter electrode 2 so as to continuously supply a common signal to the counter electrode 2. At this time, the common signal line 30 is formed of a metal film which has an excellent signal transmitting characteristic, and generally is formed of a metal film which is used for forming the gate bus line 3. The common signal line 30 includes a first section 30a which is parallel to the gate bus line 3 and is brought into contact with a predetermined portion of the counter electrode 2, and a second section 30b which extends from the first section 30a parallel to the data bus line 7 and is disposed between the counter electrode 2 and the data bus line 7. A pixel electrode 9 is formed in the unit pixel in a manner such that the pixel electrode 9 is overlapped with the counter electrode 2. At this time, the pixel electrode 9 and the counter electrode 2 are electrically insulated from each other. The pixel electrode 9 is formed to have a comb-shaped contour. The pixel electrode 9 includes comb teeth 9a which are spaced apart one from another by the same distance and parallel to the data bus line 7, and a bar section 9b which connects one ends of the comb teeth 9a and is brought into contact with a predetermined portion of the thin film transistor TFT. On the other hand, while not shown in the drawing, an upper electrode is opposed to the lower electrode 1 at a distance which is larger than a distance between the pixel electrode 9 and the counter electrode 2.
Hereinafter, a method for manufacturing the FFS-LCD constructed as mentioned above will be described. FIG. 2a is a cross-sectional view taken along the line a-a′ of FIG. 1; and FIG. 2b is a cross-sectional view taken along the line b-b′ of FIG. 1.
Referring to FIGS. 2a and 2b, after an indium tin oxide (ITO) layer is formed on the lower substrate 1, a predetermined portion of the ITO layer is patterned and thereby, the counter electrode 2 is formed. Then, after a metal film for the gate bus line, for example, a metal film made from MoW is formed on the lower substrate 1 on which the counter electrode 2 is formed, a preset portion of the metal film is patterned thereby to form the gate bus line 3 and the common electrode 30a. Thereupon, a first gate insulating film 4a made of a silicon oxynitride oxide film, a second gate insulating film 4b made of a silicon nitride film, an amorphous silicon layer and a doped semiconductor layer are sequentially deposited. Next, preselected portions of the doped semiconductor layer, the amorphous silicon layer and the second gate insulating film 4b are patterned to define a shape of an active region (a thin film transistor region). According to this, the doped semiconductor layer defines an ohmic contact layer 6, and the amorphous silicon layer defines a channel layer 5. Thereafter, a metal film for the data bus line is deposited on the lower substrate 1 on which the active region is defined, and a predetermined portion of this metal film is patterned, whereby a source electrode 7a, a drain electrode 7b, and the data bus line (not shown) are formed. Then, the ohmic contact layer 6 is patterned to define forms of the source and drain electrodes 7a and 7b, whereby the thin film transistor TFT is completed. After that, a passivation film 8 is formed on the lower substrate 1 on which the thin film transistor TFT is formed. The passivation film 8 is etched in a manner such that a predetermined portion of the drain electrode 7b is exposed. Following this, the pixel electrode 9 is formed on the passivation film 8 in a manner such that the pixel electrode 9 is brought into contact with the exposed drain electrode 7b. 
The FFS-LCD manufactured as described above operates as stated below.
If an electric field is formed between the counter electrode 2 and the pixel electrode 9, because a distance between the counter electrode 2 and the pixel electrode 9 is smaller than a distance between the upper and lower substrates, a fringe field including a vertical component is developed between the upper and lower substrates. Since the fringe field influences over entire areas on the counter electrode 2 and the pixel electrode 9, all liquid crystal molecules existing on the electrodes 2 and 9 are activated. By this, it is possible to accomplish a high aperture ratio and a high transmittance.
However, the conventional FFS-LCD has disadvantages as given below.
First, due to the fact that the first gate insulating film 4a and the passivation film 8 are intervened between the counter electrode 2 and the pixel electrode 9, the thickness of the insulation layer between the counter electrode 2 and the pixel electrode 9 is decreased and the intensity of the electric field is reduced. As a result of this, an afterimage appears on the display and driving voltage is elevated.
The common signal line 30 is formed of the same material as the gate bus line 3 to define a storage-on-common type arrangement. At this time, while the gate bus line is mainly made from MoW, the MoW has a high resistance in comparison with an aluminum-based metal film. Consequently, in order to enable a common signal to be reliably transmitted, the common signal line 30 is formed to have relatively a large width. Nevertheless, due to the fact that the common signal line 30 is formed to have relatively a large width, an aperture ratio is reduced.